1. Field of the Invention
The present invention relates generally to flash memories and in particular to flash memories having adaptive circuitry for controlling programming, reading and erasing operations.
2. Background Art
FIG. 1A shows a simplified typical conventional flash memory cell, generally designated by the numeral 10. Cell 10 is formed in an N type substrate 12. A P type well 13 is formed in substrate 12 followed by the formation of an N+ type region 16 in the well which functions as the source and another N+ type region which functions as the drain. The region 14a in the well 14 intermediate the source 16 and drain 18 region functions as the cell channel region.
A polysilicon floating gate 20 is disposed over the channel region 14a and is insulated from the channel region by a thin gate oxide 22. A polysilicon control gate 24 is disposed over the floating gate 20 and is insulated from the floating gate by an interpoly dielectric layer 26.
FIG. 1A also illustrates typical voltages which can be applied to cell 10 in order to program the cell. A relatively large positive voltage Vpp, +12 volts for example, is applied to the control gate 24. An intermediate voltage, +6 volts for example, is applied to the drain region 18 and the source region 16 is grounded. The P well 18 is biased to ground level by way of a P+ contact 28.
The large positive voltage applied to the control gate 24 causes hot electrons to be injected from the source region 16 towards the drain region 18. The electrons pass through the gate oxide 22 in that portion of the channel region 42a near the drain region 18 and into the floating gate 20. As will be explained later, the presence of the negative charge on the floating gate alters the threshold voltage of the cell thereby indicating that the cell has been programmed. Cell 10 will remain programmed until it is erased as depicted in FIG. 1B. Although the predominate mechanism for the programming mechanism is hot electron injection, other mechanisms also occur.
Referring to FIG. 1B, this figure shows typical voltages for erasing cell 10. The source region 16 and the drain region 18 are left open (floating) and an intermediate positive voltage, +3 volts for example, is applied to the P-well 14. A relatively large negative voltage Vee, typically -15 volts, is applied to the floating gate 24. These voltages cause electrons to be transferred from the floating gate 20 and through the thin gate oxide 22 and into the positive P-well along the channel 42a. The predominate mechanism for erasing in the manner previously described is commonly referred to as cold electron injection or Fowler-Nordheim tunneling. In the case of a flash memory array, all cells are usually erased in bulk, that is, individual cells are not erased. For more recent memory architectures, it is possible to erase the memory on a row by row basis.
FIG. 1C depicts the manner in which cell 10 is read. The drain region 18 is connected to an intermediate level positive voltage, such as +3 volts, by way of a load impedance represented by resistors 30A and 30B. The resistors divide down the +3 volts to approximately +1.5 volts at the drain region 18. An intermediate positive voltage, such as +3 volts, is applied to the control electrode 24 and the source region 16 is grounded.
In the event the cell 10 has not been previously programmed, the cell will have an erased threshold voltage VtErase which is relatively low. The voltage applied to the cell will be sufficient to invert the channel 14a, that is, to render the cell 10 conductive. A current will be drawn through load 30A/30B and will produce a voltage at the inverting input of a sense amplifier 32, also connected to the drain region 18, which is less than the +1.5 volts present when the cell is non-conductive at of a reference voltage VRef. The output of the sense amplifier will change state thereby indicating that the cell had not been programmed but, rather, was in the erased state.
In the event cell 10 had been previously programmed, the negative charge present on the floating gate 20 due to the presence of electrons will increase the threshold voltage of the cell. The increased threshold voltage, referred to as VtWrite, will prevent the cell 10 from becoming conductive when the voltages of FIG. 1C are applied. Thus, the voltage applied to the inverting input of amplifier 32 will remain high at +1.5 volts. Reference voltage Vref is selected to be less than +1.5 volts so the amplifier output will remain unchanged indicating that the cell had been programmed.
Cell 10 is programmed by applying the programming voltages for some period of time in the form of a programming pulse. FIG. 2 is a graph indicating programming time (in terms of microseconds) versus programmed threshold voltage VtWrite. Curves 34a and 34b represent the distribution of threshold voltage VtWrite among a population of cells for a given program pulse width. It can be seen from these curves that there is a fairly wide distribution of threshold voltages VtWrite for short programming pulses with the two curves 34a and 34b converging at a higher voltage when the pulse width is on the order of a 100 microseconds or more.
FIG. 3 is a graph showing the distribution of erase threshold voltages VtErase versus time in terms of milliseconds. Curves 36a and 36b represent the distribution of erase threshold voltages VtErase for a population of cells. As can be seen, the distribution becomes somewhat smaller and the absolute voltage less as the duration of the erase pulse increases.
FIG. 4 is a further graph, with the horizontal axis representing the threshold voltage Vt and the vertical axis representing the number of cells in a memory array expressed in terms of Bytes. Curve 38a depicts the distribution of erase threshold voltages VtErase for a population of erased cells in a particular memory array. All threshold voltages fall between a minimum value VtE1 and a maximum value VtE2, with the majority of cells falling approximately midrange between the two.
Curve 38b of FIG. 4 depicts the distribution of write (program) threshold voltage VtWrite for a population of programmed cells. All threshold voltages fall between a minimum value VtW1 and a maximum value VtW2, with the majority of cells falling approximately midrange between the two values.
Curve 40 of FIG. 4 represents the reference voltage VSense which is related to reference voltage VRef (FIG. 1C) which is used to sense whether a cell has been programmed during a read operation. Ideally, the entire population of all cells in an array has a single fixed threshold voltage VtErase and a single fixed threshold voltage VtWrite which is greater than VtErase by some fixed magnitude so that the programmed state of the cells can be reliably ascertained. Further, in order to increase the speed of cell read operations, ideally this difference in threshold voltage magnitude is relatively small so that the time required to sense the state of a cell is reduced. Such reduction comes about due to the fact that inherent time constants in the cell sensing circuitry result in read delays which can be reduced provided the magnitude of the voltage swings required for sensing are reduced.
Notwithstanding the foregoing, it can be seen from the curves of FIGS. 2, 3 and 4 that the average value of threshold voltages VtErase and VtWrite vary as does the distribution of the population of cells around these average values. This is due primarily to large process variations and wide operating conditions. These factors interfere with reliable memory operation. For example, if a single cell in an array has a threshold voltage VtErase that has been reduced to 0 volts, that is, VtE1 is 0 volts or less, the cell will remain conductive even in the absence of a read voltage being applied to the control gate. This condition will interfere with the proper operation of the entire array. Similarly, if a single cell has a threshold voltage VtErase which exceeds the sense voltage Vsense, that is, VtE2 is on the other side of curve 40 (FIG. 4), the cell will be improperly interpreted as a programmed cell during a read operation.
The above-noted problems become much more severe in low voltage applications such as +3 volt battery operation. In that event, the distribution curve 38a must be even more precisely controlled, as compared with +5 volt operation, since Vsense will typically be only approximately +5 volts.
The present invention overcomes the above-described shortcomings of conventional flash memories. The disclosed memory permits the threshold voltages VtErase and VtWrite be adaptively controlled to compensate for process variations and wide changes in operating conditions. In addition, the reference voltage VRef can be adaptively adjusted to compensate these variations and conditions. These and other advantages of the present invention will become apparent to those skilled in the art upon a review of the following Detailed Description of the Invention together with the drawings.